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SyncMOS Technologies International. Inc.
Product List
SM79164V16J/Q,16MHz 64KB internal flash MCU SM79164L20P, 20MHz 64KB internal flash MCU SM79164L25J/Q, 25MHz 64KB internal flash MCU SM79164C25P, 25MHz 64KB internal flash MCU SM79164C35J/Q, 35MHz 64KB internal flash MCU
SM79164
8 - Bit Micro-controller
with 64KB flash & 4KB RAM embedded
Features
2.4V ~ 3.0V For V Version Working voltage: 3.0V ~ 3.6V For L Version 4.5V ~ 5.5V For C Version General 8052 family compatible 12 clocks per machine cycle 64K byte on chip program flash 4096 byte on-chip data RAM Three 16 bit Timers/Counters One Watch Dog Timer Four 8-bit I/O ports for PDIP package Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP package Full duplex serial channel Bit operation instruction Industrial Level 8-bit Unsigned Division 8-bit Unsigned Multiply BCD arithmetic Direct Addressing Indirect Addressing Nested Interrupt Two priority level interrupt A serial I/O port Power save modes: Idle mode and Power down mode Code protection function Low EMI (inhibit ALE) Bank mapping direct addressing mode for access on-chip RAM 8 channel PWM function with P1.0 ~ P1.7
Description
The SM79164 series product is an 8 - bit single chip micro controller with 64KB on-chip flash and 4K byte RAM embedded. It is a derivative of the 8052 micro controller family. It has 8-channel PWM build-in. User can access on-chip expanded RAM with easier and faster way by its `bank mapping direct addressing mode' scheme. With its hardware features and powerful instruction set, it's straight forward to make it a versatile and cost effective controller for those applications which demand up to 32 I/O pins for PDIP package or up to 36 I/O pins for PLCC/QFP package, or applications which need up to 64K byte flash memory for program data. To program the on-chip flash memory, a commercial writer is available to do it in parallel programming method.
Ordering Information
yywwv SM79164ihhkL yy: year, ww:month v: version identifier {, A, B,...} i:process identifier {V=2.4V~3.0V, L=3.0V ~ 3.6V, C=4.5V ~ 5.5V} hh: working clock in MHz {20, 25, 35} k: package type postfix {as below table} L:PB free identifier No text is Non- PB free ,"P" is PB free
Pin/Pad Configuration page 2 page 2 page 2
Postfix P J Q
Package 40L PDIP 44L PLCC 44L QFP
Dimension page 21 page 22 page 23
Taiwan 6F, No. 10-2 Li - Hsinchu First Road , Science-based Industrial Park, Hsinchu, Taiwan 30078 TEL: 886-3-5671820 886-3-5671880 FAX: 886-3-5671891 886-3-5671894
Web site: http://www.syncmos.com.tw
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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Pin Configurations
P1.1/T2EX/PWM1 P1.0/T2/PWM0 P4.2 VDD P0.0/AD0 P0.1/AD1
SM79164
P0.7/AD7 #EA
P2.7/A15
P1.4/PWM4
P1.3/PWM3 P1.2/PWM2
P0.2/AD2
P0.3/AD3
6
5
4
32
1 44 43 42 41 40
39 38 37 36 35 34 33 32 31 30 29
PWM5/P1.5 PWM6/P1.6 PWM7/P1.7 RES RXD/P3.0 P4.3 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5
7 8 9 10 11 12 13
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA P4.1 ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13
AD3/P0.3 AD2/P0.2 AD1/P0.1 AD0/P0.0 VDD P4.2 T2/PWM0/P1.0 T2EX/PWM1/P1.1 PWM2/P1.2 PWM3/P1.3 PWM4/P1.4
34 35 36 37 38 39 40 41 42 43 44
33 32 31 30 29 28 27 26 25 24 23 22 21
ALE
P2.6/A14 P2.5/A13
P0.4/AD4
P0.5/AD5
P0.6/AD6
P4.1
#PSEN
P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P4.0 VSS XTAL1 XTAL2 P3.7/#RD P3.6/#WR
SM79164 ihhJ 44L PLCC
SM79164 ihhQ 44L QFP
(Top View)
20 19 18 17 16 15 14 13 12
14 (Top View) 15 16 17 18 19 20 21 22 23 24 25 26 27 28
1
2
3
4
5
6
7
8
9
10 11
#WR/P3.6
#RD/P3.7 XTAL2 XTAL1 VSS
A10/P2.2
A11/P2.3
A12/P2.4
A8/P2.0
A9/P2.1
P4.0
PWM5/P1.5
TXD/P3.1
T0/P3.4
P4.3
PWM6/P1.6 PWM7/P1.7 RES
RXD/P3.0
PWM0/T2/P1.0 PWM1/T2EX/P1.1 PWM2/P1.2 PWM3/P1.3 PWM4/P1.4 PWM5/P1.5 PWM6/P1.6 PWM7/P1.7 RES RXD/P3.0 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 #WR/P3.6 #RD/P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
7 8
9 10 11
12
13 14 15 16 17 18 19 20
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T1/P3.5
SM79164ihhP 40L PDIP
(Top View)
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SM79164
Block Diagram
Timer 1 Stack Pointer Decoder & Register 4096 bytes RAM
Timer 2
Timer 0
WDT
RES Reset Circuit to pertinent blocks Acc to whole chip Buffer2 Buffer1
Buffer
DPTR
Vdd Vss Power Circuit
PC Incrementer
Interrupt Circuit
to pertinent blocks ALU
Program Counter
Register XTAL2 XTAL1 #EA ALE #PSEN Timing Generator to whole system FFFFH PSW
Instruction Register
64K bytes Flash Memory
Port 0 Latch 8
PWM
Port 1 Latch
Port 2 Latch
Port 3 Latch
Port 4 Latch
0000H Port 0 Driver & Mux 8 Port 1 Driver & Mux Port 2 Driver & Mux Port 3 Driver & Mux 8 Port 4 Driver & Mux 4
8
8
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Pin Descriptions
40L 44L 44L PDIP QFP PLCC Pin# Pin# Pin#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 40 41 42 43 44 1 2 3 4 5 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 38 17 28 39 6 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 44 23 34 1 12
Symbol
P1.0/T2/PWM0 P1.1/T2EX/PWM1 P1.2/PWM2 P1.3/PWM3 P1.4/PWM4 P1.5/PWM5 P1.6/PWM6 P1.7/PWM7 RES P3.0/RXD P3.1/TXD P3.2/#INT0 P3.3/#INT1 P3.4/T0 P3.5/T1 P3.6/#WR P3.7/#RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 #PSEN ALE #EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD P4.0 P4.1 P4.2 P4.3
Active I/O
i/o i/o i/o i/o i/o i/o i/o i/o i i/o i/o i/o i/o i/o i/o i/o i/o o i i/o i/o i/o i/o i/o i/o i/o i/o o o i i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o
Names
bit 0 of port 1 & timer 2 clock out , PWM channel 0 bit 1 of port 1 & timer 2 control , PWM channel 1 bit 2 of port 1 & PWM channel 2 bit 3 of port 1 & PWM channel 3 bit 4 of port 1 & PWM channel 4 bit 5 of port 1 & PWM channel 5 bit 6 of port 1 & PWM channel 6 bit 7 of port 1 & PWM channel 7 Reset bit 0 of port 3 & Receive data bit 1 of port 3 & Transmit data bit 2 of port 3 & low true interrupt 0 bit 3 of port 3 & low true interrupt 1 bit 4 of port 3 & Timer 0 bit 5 of port 3 & Timer 1 bit 6 of port 3 & ext. memory write bit 7 of port 3 & ext. mem. read Crystal out Crystal in Sink Voltage, Ground bit 0 of port 2 & bit 8 of ext. memory address bit 1 of port 2 & bit 9 of ext. memory address bit 2 of port 2 & bit 10 of ext. memory address bit 3 of port 2 & bit 11 of ext. memory address bit 4 of port 2 & bit 12 of ext. memory address bit 5 of port 2 & bit 13 of ext. memory address bit 6 of port 2 & bit 14 of ext. memory address bit 7 of port 2 & bit 15 of ext. memory address program storage enable address latch enable external access bit 7 of port 0 & data/address bit 7 of ext. memory bit 6 of port 0 & data/address bit 6 of ext. memory bit 5 of port 0 & data/address bit 5 of ext. memory bit 4 of port 0 & data/address bit 4 of ext. memory bit 3 of port 0 & data/address bit 3 of ext. memory bit 2 of port 0 & data/address bit 2 of ext. memory bit 1 of port 0 & data/address bit 1 of ext. memory bit 0 of port 0 & data/address bit 0 of ext. memory Drive Voltage, +5 Vcc bit 0 of Port 4 bit 1 of Port 4 bit 2 of Port 4 bit 3 of Port 4
H
L/ L/ -
L
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Special Function Register (SFR)
The address $80 to $FF can be accessed by direct addressing mode only. Address $80 to $FF is SFR area. The following table lists the SFRs which are identical to general 8052, as well as SM79164 Extension SFRs.
Special Function Register (SFR) Memory Map
$F8 $F0 $E8 $E0 $D8 $D0 $C8 $C0 $B8 $B0 $A8 $A0 $98 $90 $88 $80 ACC P4 PSW T2CON IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TL1 DPH TH0 (Reserved) TH1 RCON DBANK PCON SBUF P1CON WDTC WDTKET T2MOD RCAP2L PWMC4 PWMC0 RCAP2H PWMD4 PWMD0 PWMC5 PWMC1 TL2 PWMD5 PWMD1 PWMC6 PWMC2 TH2 PWMD6 PWMD2 PWMD7 PWMD3 SCONF PWMC7 PWMC3 B $FF $F7 $EF $E7 $DF $D7 $CF $C7 $BF $B7 $AF $A7 $9F $97 $8F $87
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM79164
Addr 85H 86H 97H 9BH 9FH B3H B4H B5H B6H BBH BCH BDH BEH SFR RCON DBANK WDTKEY P1CON WDTC PWMD0 PWMD1 PWMD2 PWMD3 PWMD4 PWMD5 PWMD6 PWMD7 Reset 00H 0*000001 00H 00H 0*0**000 00H 00H 00H 00H 00H 00H 00H 00H BSE PWME7 WDTE PWMD07 PWMD17 PWMD27 PWMD37 PWMD47 PWMD57 PWMD67 PWMD77 PWME6 Reserve PWMD06 PWMD16 PWMD26 PWMD36 PWMD46 PWMD56 PWMD66 PWMD76 BS5 PWME5 CLEAR PWMD05 PWMD15 PWMD25 PWMD35 PWMD45 PWMD55 PWMD65 PWMD75 PWMD04 PWMD14 PWMD24 PWMD34 PWMD44 PWMD54 PWMD64 PWMD74 PWMD03 PWMD13 PWMD23 PWMD33 PWMD43 PWMD53 PWMD63 PWMD73 BS4 PWME4 7 6 5 4 3 RAMS3 BS3 PWME3 2 RAMS2 BS2 PWME2 PS2 PWMD02 PWMD12 PWMD22 PWMD32 PWMD42 PWMD52 PWMD62 PWMD72 1 RAMS1 BS1 PWME1 PS1 PWMD11 0 RAMS0 BS0 PWME0 PS0 PWMD10
WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEY0
PWMD01 PWMD00 PWMD21 PWMD20 PWMD31 PWMD30 PWMD41 PWMD40 PWMD51 PWMD50 PWMD61 PWMD60 PWMD71 PWMD70
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Addr BFH C8H C9H D3H D4H D5H D6H DBH DCH DDH DEH D8H
SFR SCONF T2CON T2MOD PWMC0 PWMC1 PWMC2 PWMC3 PWMC4 PWMC5 PWMC6 PWMC7 P4
Reset 0*****00 00H ******00 *****000 *****000 *****000 *****000 *****000 *****000 *****000 *****000 ****1111
7 WDR TF2
6 EXF2
5 RCLK
4 TCLK
3 EXEN2
2 TR2 PBS0 PBS1 PBS2 PBS3 PBS4 PBS5 PBS6 PBS7
1 OME C/T2 T2OE PFS01 PFS11 PFS21 PFS31 PFS41 PFS51 PFS61 PFS71 P4.1
0 ALEI CP/RL2 DCEN PFS00 PFS10 PFS20 PSF30 PFS40 PFS50 PFS60 PSF70 P4.0
P4.3
P4.2
Extension Function Description
1. Memory Structure
The SM79164 is the general 8052 hardware core as a single chip micro controller. Its memory structure follows general 8052 structure.
1.1 Program Memory
The SM79164 has 64K byte on-chip flash memory which used as general program memory. The address range for the 64K byte is $0000 to $FFFF. FFFF
64K Program memory space
0000 Note: The single flash block address structure for doing as well as program ROM flash.
1.2 Data Memory
The SM79164 has 4K bytes on-chip RAM, 256 bytes of it are the same as general 8052 internal memory structure while the expanded 3840 bytes on-chip RAM can be accessed by external memory addressing method (by instruction MOVX), or by `Bank mapping direct addressing mode' as described in page 8.
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0EFF
FF Higher 128 bytes (Access by 80 indirect addressing mode only) 7F
SFR (Accessed by direct addressing mode only)
Expanded 3840 bytes RAM (Accessed by direct external addressing mode, by instruction MOVX, or by Bank mapping direct addressing mode) FF (OME = 1)
Lower 128 bytes (Accessed by
80
0000
direct & indirect addressing mode) 00
On-chip expanded RAM address structure.
1.2.1 Data Memory - Lower 128 byte ($00 to $7F, Bank 0 & Bank 1)
Data Memory $00 to $FF is the same as 8052. The address $00 to $7F can be accessed by direct and indirect addressing modes. Address $00 to $1F is register area. Address $20 to $2F is memory bit area. Address $30 to $7F is for general memory area.
1.2.2 Data Memory - Higher 128 byte ($80 to $FF, Bank 2 & Bank 3)
The address $80 to $FF can be accessed by indirect addressing mode or by bank mapping direct addressing mode. Address $80 to $FF is data area.
1.2.3 Data Memory - Expanded 3840 bytes ($0000 to $0EFF, Bank 4 ~ Bank 63)
From external address $0000 to $0EFF is the on-chip expanded RAM area, total 3840 bytes. This area can be accessed by external direct addressing mode (by instruction MOVX) or by bank mapping direct addressing mode as described below:
1.3 Bank mapping direct addressing mode:
We provide RAM bank address `40H~7FH' as mapping window which allow user access all the 4KB on-chip RAM through this RAM bank address. That means using direct addressing mode can access all the 4KB on-chip RAM. Please see next page for the mapping mode table.
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BS5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
BS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
BS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1
BS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 1
BS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1
040h ~ 07fh mapping address 000h ~ 03fh 040h ~ 07fh 080h ~ 0bfh 0c0h ~ 0ffh 0000h ~ 003fh 0040h ~ 007fh 0080h ~ 00bfh 00c0h ~ 00ffh 0100h ~ 013fh 0140h ~ 017fh 0180h ~ 01bfh 01c0h ~ 01ffh 0200h ~ 023fh 0240h ~ 027fh 0280h ~ 02bfh 02c0h ~ 02ffh 0300h ~ 033fh 0340h ~ 037fh 0380h ~ 03bfh 03c0h ~ 03ffh 0400h ~ 043fh 0440h ~ 047fh 0480h ~ 04bfh 04c0h~04ffh 0d40h ~ 0d7fh 0d80h ~ 0dbfh 0dc0h ~ 0dffh 0e00h ~ 0e3fh 0e40h ~ 0e7fh 0e80h ~ 0ebfh 0ec0h ~ 0effh
Note lower 128 byte RAM lower 128 byte RAM higher 128 byte RAM higher 128 byte RAM on-chip expanded 3840 byte RAM " " " " " " " " " " " " " " " " " " " " " " " " " "
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With this bank mapping scheme, user can access entire 4k byte on-chip RAM with direct addressing method. That means using the window area ($040~$07F), user can access any bank (64 byte) data of 4k byte on-chip RAM space which is selected by BS[5:0] of data bank control register (DBANK, $86). For example, user write #30h to $101 address: MOV DBANK, #88H ; set bank mapping $040~$07f to $0100~$013f MOV A, #30H ; store #30H to A MOV 41H, A ; write #30H to $0101 address
Data Bank Control Register (DBANK, $86)
bit-7 BSE Read / Write: Reset value: R/W 0 Unused * BS5 R/W 0 BS4 R/W 0 BS3 R/W 0 BS2 R/W 0 BS1 R/W 0 bit-0 BS0 R/W 1
Data bank select enable bit BSE = 1 enables the data bank select function Data bank select enable bit BSE = 0 disables the data bank select function BS[5:0] setting will map $040~$07F RAM space to entire 4k byte on-chip RAM space.
Internal RAM Control Register (RCON, $85)
bit-7 Unused Read / Write: Reset value: * Unused * Unused * Unused * RAMS3 R/W 0 RAMS2 R/W 0 RAMS1 R/W 0 bit-0 RAMS0 R/W 0
SM79164 has 3840 byte on-chip RAM which can be accessed by external memory addressing method only. (By instruction MOVX). The address space of instruction MOVX @Rn is determined by bit 3, bit2, bit1, bit 0 (RAMS3, RAMS2, RAMS1, RAMS0) of RCON. The default setting of RAMS3, RAMS2, RAMS1, RAMS0 bits is 0000 (page0).
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RAMS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
RAMS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
RAMS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
RAMS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
MOVX @Ri i=0,1 mapping to expended RAM address $0000 ~ $00FF $0100 ~ $01FF $0200 ~ $02FF $0300 ~ $03FF $0400 ~ $04FF $0500 ~ $05FF $0600 ~ $06FF $0700 ~ $07FF $0800 ~ $08FF $0900 ~ $09FF $0A00 ~ $0AFF $0B00 ~ $0BFF $0C00 ~ $0CFF $0D00 ~ $0DFF $0E00 ~ $0EFF
The port 0, port2, port3.6 and port3.7 can be used as general purpose I/O pin while port0 is open-drain structure.
System Control Register (SCONF, $BF)
bit-7 WDR Read / Write: Reset value: R/W 0 Unused * Unused * Unused * Unused * Unused * OME R/W 0 bit-0 ALEI R/W 0
WDR : Watch Dog Timer Reset. OME : 3840 bytes on-chip RAM enable bit ALEI : ALE output inhibit bit, to reduce EMI Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin. The bit 1 (OME) of SCONF can enable or disable the on-chip expanded 3840 byte RAM. The default setting of OME bit is 0 (disable). The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened.
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1.4 I/O Pin Configuration
The ports 1, 2 and 3 of standard 8051 have internal pull-up resistor, and port 0 has open-drain outputs. Each I/O pin can be used independently as an input or an output. For I/O ports to be used as an input pin, the port bit latch must contain a `1' which turns off the output driver FET. Then for port 1, 2 and 3 port pin is pulled high by a weak internal pull-up, and can be pulled low by an external source. The port 0 has open-drain outputs which means its pull-ups are not active during normal port operation. Writing `1' to the port 0 bit latch will causing bit floating so that it can be used as a high-impedance input. The port 4 used as GPIO will has the same function as port 1, 2 and 3.
output data
pin
port 0 standard 8051
output data
port 1, 2 and 3 standard 8051
pin
input data
input data
2. Port 4 for PLCC or QFP package:
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Port4 (P4, $D8)
bit-7 Unused Read / Write: Reset value: * Unused * Unused * Unused * P4.3 R/W 1 P4.2 R/W 1 P4.1 R/W 1 bit-0 P4.0 R/W 1
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.
3. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. User should check WDR bit of SCONF register whenever un-predicted reset happened. The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway. There is a 250KHz RC oscillator embedded in chip. Set WDTE = "1" will enable the RC oscillator and the frequency is independent to the system frequency. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM79164 been reset, either hardware reset or WDT reset. To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning.
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3.1 Watch Dog Timer Registers: Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
bit-7 WDTE Read / Write: Reset value: R/W 0 Reserve * CLEAR R/W 0 Unused * Unused * PS2 R/W 0 PS1 R/W 0 bit-0 PS0 R/W 0
WDTE : Watch Dog Timer enable bit CLEAR : Watch Dog Timer reset bit PS[2:0] : Overflow period select bits PS [2:0] 000 001 010 011 100 101 110 111 Overflow Period (ms) 2.048 4.096 8.192 16.384 32.768 65.536 131.072 262.144
Watch Dog Key Register - (WDTKEY, $97H)
bit-7 WDT KEY7 Read / Write: Reset value: W 0 WDT KEY6 W 0 WDT KEY5 W 0 WDT KEY4 W 0 WDT KEY3 W 0 WDT KEY2 W 0 WDT KEY1 W 0 bit-0 WDT KEY0 W 0
By default, the WDTC is read only. User need to write values 1EH, E1H sequentially to the WDTKEY($97H) register to enable the WDTC write attribute, That is MOV WDTKEY, # 1EH MOV WDTKEY, # E1H When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY($97H) register to disable the WDTC write attribute, That is MOV WDTKEY, # E1H MOV WDTKEY, # 1EH
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Watch Dog Timer Register - System Control Register (SCONF, $BF)
bit-7 WDR Read / Write: Reset value: R/W 0 Unused * Unused * Unused * Unused * Unused * OME R/W 0 bit-0 ALEI R/W 0
The bit 7 (WDR) of SCONF is Watch Dog TImer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever un-predicted reset happened
4. Reduce EMI Function
The SM79164 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will inhibit the clock signal in Fosc/6Hz output to the ALE pin.
5. Pulse Width Modulation (PWM)
The Pulse Width Modulation (PWM) module contains 1 kind of PWM sub module: PWM. PWM also has four 8-bit channels.
5.1 PWM Function Description:
Each PWM channel contains a 8-bit wide PWM data register (PWMDR) to decide number of continuous pulses within a PWM frame cycle. The value programmed in the register will determine the pulse length of the output. The PWM channel can be configured as 5-bit or 8-bit resolution. If a channel is configured as 5-bit resolution, only LSB 5 bits are available. The value of each PWM Data Register (PWMDR) is continuously compared with the content of an internal counter to determine the state of each PWM channel output pin.
5.2 PWM Registers - P1CON[7:0], PWMC[7:0], PWMD[7:0] PWM Registers - Port1 Configuration Register (P1CON, $9B)
PWME7 Read / Write: Reset value: R/W 0
PWME6 R/W 0
PWME5 R/W 0
PWME4 R/W 0
PWME3 R/W 0
PWME2 R/W 0
PWME1 R/W 0
PWME0 R/W 0
PWM[7:0]E: When the bit set to one, the corresponding PWM pin is active as PWM function. When the bit reset to zero, the corresponding PWM pin is active as I/O pin. Five bits are cleared upon reset.
PWM Registers - PWM Control Register (PWMC[7:0], $DE ~ $DB, $D6 ~ $D3)
bit-7 Unused Read / Write: Reset value: * Unused * Unused * Unused * Unused * PBS[7:0] R/W 0 PFS[7:0]1 R/W 0 bit-0 PFS[7:0]0 R/W 0
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PFS[7:0][1:0] : These two bits is 2's power parameter to form a frequency divider for input clock. PBS[7:0] : This bit decides channel bit resolution. If PBS[7:0] is set, the channel is 5-bit resolution.
PFS[7:0]1 PFS[7:0]0
Divider 0.5 1 2 4
PWM clock, Fosc=12MHz 24MHz (note) 12MHz 6MHz 3KHz
PWM clock, Fosc=24MHz 48MHz (note) 24MHz 12MHz 6MHz
0 0 1 1
0 1 0 1
note : If X'tal > 24MHz, can not select PFS[1:0] = 00
PWM Registers - PWM Data Register (PWMD[7:0], $BE ~ $BB, $B6 ~ $B3)
bit-7 PWMD [7:0]7 Read / Write: Reset value: R/W 0 PWMD [7:0]6 R/W 0 PWMD [7:0]5 R/W 0 PWMD [7:0]4 R/W 0 PWMD [7:0]3 R/W 0 PWMD [7:0]2 R/W 0 PWMD [7:0]1 R/W 0 bit-0 PWMD [7:0]0 R/W 0
PWM[7:0][7:0] : content of PWM Data Register. If PBS[7:0] is set, only PWM[7:0][4:0] are available.]
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Example of PWM timing diagram:
For 5-bit resolution channel, M = content of PWMD[7:0]: M = $00
32T
M = $01
M = $0F M = $1F
PWM Clock Frequency = 1/T = Fosc / Divider The PWM output cycle frame frequency = PWM Clock frequency / 32 For 8-bit resolution channel: M = $00
256T
M = $01
M = $7F
M = $FF
PWM Clock Frequency = 1/T = Fosc / Divider The PWM output cycle frame frequency = PWM Clock frequency / 256
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Operating Conditions
Symbol TA VCC Fosc35 Description Operating temperature Supply voltage Oscillator Frequency Min. -40 2.4 3.0 Typ. 25 Max. 85 5.5 35 Unit.
o
Remarks Ambient temperature under bias Note1
C V
MHz Note2
Note1:Operating Voltage {V=2.4V ~ 3.0V, L=3.0V ~ 3.6V, C=4.5V ~ 5.5V} Note2:Working Frequency {V=16MHZ for J/Q package,L=20MHZ for P package,L=25MHZ for J/Q package,C=25MHZ for P package,C=35MHZ for J/Q package}
DC Characteristics
(TA = -40 degree C to 85 degree C, Vcc = 2.4V to 5.5V) Symbol
VIL1 VIL2 VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 IIL ITL ILI R RES C IO I CC
Parameter
Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Logical 0 Input Current Logical Transition Current Input Leakage Current Reset Pulldown Resistance Pin Capacitance Power Supply Current
Valid
port 0,1,2,3,4,#EA RES, XTAL1 port 0,1,2,3,4,#EA RES, XTAL1 port 0, ALE, #PSEN port 1,2,3,4 port 0 port 1,2,3,4,ALE,#PSEN port 1,2,3,4 port 1,2,3,4 port 0, #EA RES Vdd
Min. -0.5 0 2.0 70%Vcc
Max. 0.8 0.8 Vcc+0.5 Vcc+0.5 0.45 0.45
Unit V V V V V V V V V V uA uA uA Kohm pF mA mA uA
Test Conditions
2.4 90%Vcc 2.4 90%Vcc -75 -650 + 10 300 10 20 6.5 50
IOL=3.2mA IOL=1.6mA IOH=-800uA (only for VCC=5V) IOH=-80uA IOH=-60uA (only for VCC=5V) IOH=-10uA Vin=0.45V Vin=2.0V 0.45V50
Note1: Under steady state (non-transient) conditions, IOL must be externally Limited as follows: Maximum IOL per port pin : 10mA Maximum IOL per 8-bit port : port 0 :26mA port 1,2,3 :15mA Maximum total IOL for all output pins : 71mA If IOL exceeds the condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. Note2 : Minimum VCC for Power-down is 2V.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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AC Characteristics
(20/25MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=100pF; CL for all Other Output=80pF) Symbol T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLYL T AVYL T QVWH T QVWX T WHQX T RLAZ T YALH T CHCL T CLCX T CLCH T CHCX T, TCLCL Parameter ALE pulse width Address Valid to ALE low Address Hold after ALE low ALE low to Valid Instruction In ALE low to #PSEN low #PSEN pulse width #PSEN low to Valid Instruction In Instruction Hold after #PSEN Instruction Float after #PSEN Address to Valid Instruction In #PSEN low to Address Float #RD pulse width #WR pulse width #RD low to Valid Data In Data Hold after #RD Data Float after #RD ALE low to Valid Data In Address to Valid Data In ALE low to #WR High or #RD low Address Valid to #WR or #RD low Data Valid to #WR High Data Valid to #WR transition Data hold after #WR #RD low to Address Float #WR or #RD high to ALE high clock fall time clock low time clock rise time clock high time clock period Valid Cycle RD/WRT RD/WRT RD/WRT RD RD RD RD RD RD RD RD RD WRT RD RD RD RD RD RD/WRT RD/WRT WRT WRT WRT RD RD/WRT fosc=16MHz Min. Typ. Max 115 43 53 240 53 173 177 0 87 292 10 365 365 302 0 145 590 542 178 197 230 403 38 73 53 Variable fosc Unit Min. Typ. Max 2xT - 10 nS T - 20 nS T - 10 nS 4xT - 10 nS T - 10 nS 3xT - 15 nS 3xT - 10 nS 0 nS T + 25 nS 5xT - 20 nS 10 nS 6xT - 10 nS 6xT - 10 nS 5xT - 10 nS 0 nS 2xT + 20 nS 8xT - 10 nS 9xT - 20 nS 3xT - 10 3xT + 10 nS 4xT - 20 nS 7xT - 35 nS T - 25 nS T + 10 nS 5 nS 72 T -10 T + 10 nS nS nS nS nS 1/fosc nS Vcc
SM79164
Remarks
63
ICC Active mode test circuit Vcc VCC RST SM79164 PO EA
ICC
8
(NC) Clock Signal
XTAL2 XTAL1 VSS
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Application Reference Valid for SM79164
X'tal C1 C2 R X'tal C1 C2 R 3MHz 30 pF 30 pF open 16MHz 30 pF 30 pF open 6MHz 30 pF 30 pF open 25MHz 15 pF 15 pF 62K 9MHz 30 pF 30 pF open 33MHz 5 pF 5 pF 6.8K 12MHz 30 pF 30 pF open
XI X'tal
SM79164 SM79164
R X2 C1 C2
NOTE: Oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. User should check with the crystal or ceramic resonator manufacturer for appropriate value of external components.
Data Memory Read Cycle Timing
T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3
OSC
ALE
#PSEN
#RD
PORT2
ADDRESS A15 - A8
PORT0
INST in Float
A7 - A0
Float
DATA in
Float ADDRESS or Float
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Program Memory Read Cycle Timing
T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2
OSC
ALE
#PSEN #RD,#WR
PORT2
ADDRESS A15 - A8
ADDRESS A15 - A8
PORT0
Float
A7 - A0
Float
INST in
Float
A7 - A0
Float
INST in
Float
Data Memory Write Cycle Timing
T12 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T1 T2 T3
OSC
ALE
#PSEN
#WR
PORT2
ADDRESS A15 - A8
PORT0
INST
Float
A7 - A0
DATA OUT
ADDRESS or Float
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I/O Ports Timing
T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 T4 T5 T6 T7 T8
X1 inputs P0,P1
sampled
sampled
inputs P2,P3 Output by Mov Px,Src RxD at Serial Port Shift Clock (Mode 0)
current data next data
sampled
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
70%Vdd
0.45V
20%Vdd-0.1V TCHCL TCLCX TCLCH TCHCX
Tm.I
#PSEN ALE PORT 0
External Program Memory Read Cycle
TPLPH
TLHLL TAVLL A0 - A7
TLLPL TLLAX TPLAZ TPLIV
TPXIZ TPXIX Instruction. IN A0 - A7
TAVIV
PORT 2
A8 - A15
A8 - A15
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Tm.II
External Data Memory Read Cycle
#PSEN
TYHLH
ALE
TLLDV TLLYL TRLRH
#RD
TAVLL TLLAX TRLAZ A0 - A7 from Ri or DPL TAVYL TAVDV TRLDV TRHDZ TRHDX DATA IN A0 - A7 from PCL INSTRL IN
PORT 0
PORT 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
Tm.III External Data Memory Write Cycle
#PSEN
TLHLL
TYHLH
ALE
TLLYL TWLWH
#WR
TAVLL TLLAX
TQVWX
TWHQX TQVWH
PORT 0
A0-A7 from Ri or DPL
DATA OUT
A0-A7 From PCL
INSTRL IN
TAVYL
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
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PDIP 40L (600mil) Package Information
SM79164
D im e n s io n in m m S ym b ol M in A1 A2 b b1 b2 b3 c c1 D E N o te : 1. 2. R efer to JE D E C S T D .M S -0 1 1 (A C ). D im e n sio n D a n d E 1 d o n o t in c lu d e m o ld p ro tru s io n . A llo w ab le p ro tru s io n is 0 .2 5 m m p er s id e. D a n d E 1 a re m a x im u m p la s tic b o d y siz e d im e n s io n in clu d e m o ld m is m a tc h . 3. D im e n sio n b 3 d o e s n o t in clu d e d am b ar p ro tru s io n . A llo w ab le d a m b a r p ro tru sio n s h a ll n o t c a u s e th e le ad w id th to e x c e e d th e m a x im u m b 3 d im en sio n b y m o re th a n 0 .2 m m . L S Q1 2 .9 2 1 1 .7 2 7 1 .6 5 1 0 3 .3 0 2 1 .9 8 1 1 .7 7 8 3 .6 8 3 2 .2 3 5 1 .9 0 5 10 E1 e eB 0 .2 5 4 3 .6 8 3 0 .3 5 6 0 .3 5 6 1 .0 1 6 1 .0 1 6 0 .2 0 3 0 .2 0 3 5 2 .0 7 1 4 .9 9 1 3 .6 9 1 5 .7 5 N om 3 .8 1 0 0 .5 0 0 0 .4 5 7 1 .2 7 0 1 .3 2 1 0 .2 5 4 0 .2 5 4 5 2 .2 1 5 .2 4 1 3 .8 7 2 .5 4 0 1 6 .2 6 M ax 3 .9 3 7 0 .6 6 0 0 .5 0 8 1 .5 2 4 1 .6 2 6 0 .4 3 2 0 .3 5 6 5 2 .3 2 1 5 .4 9 1 3 .9 4 1 6 .7 6
D im e n s io n in M IL M in 10 145 14 14 40 40 8 8 2050 590 539 620 115 68 65 0 N om 150 20 18 50 52 10 10 2055 600 546 100 640 130 78 70 M ax 155 26 22 60 64 17 14 2060 610 549 660 145 88 75 10
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PLCC 44L Package Information
SM79164
UNIT SYMBOL A A1 A2 B
INCH(REF)
0.180(MAX) 0.024 0.005 0.105 0.005 0.018 + 0.004 - 0.002 0.028 + 0.004
MM(BASE)
4.572(MAX) 0.52 0.14 2.667 0.127 0.457 + 0.102 - 0.051 0.711 + 0.102 - 0.051 0.254(TYP) 17.526 0.254 16.586 0.076 15.494 0.508 17.526 0.254 16.586 0.076 15.494 0.254 1.270(TYP) 0.076(MAX) 0~5
B1 c D D1 D2 E E1 E2 e y
Specifications subject to change without notice,contact your sales representatives for the most recent information.
- 0.002 0.010(TYP) 0.690 0.010 0.653 0.003 0.610 0.020 0.690 0.010 0.653 0.003 0.610 0.010 0.050(TYP) 0.003(MAX) 0~5
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Q F P 4 4 L ( 1 0 x 1 0 x 2 .0 m m ) P a c k a g e I n fo r m a t io n
Dimension in mm Symbol Min A A1 A2 b b1 c
Note: 1. 2. Refer to JEDC STD.MS-022(AB). Dimension E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side.E1 are maximum plastic body size dimension include mold mismatch . 3. Dimension b does not include dambar 0.05 1.90 0.29 0.29 0.11 0.11 13.00 9.90 0.73 1.50 0
Dimension in MIL Min
2.1 74.8 11.4 11.4 4.3 4.3 512 390 28.7 59.1 0
Nom
0.15 2.00 0.32 0.30 0.17 0.15 13.20 10.00 0.800 0.88 1.60
Max
2.45 0.25 2.10 0.45 0.41 0.23 0.19 13.40 10.10 1.03 1.70 0.076 7
Nom
6.0 78.7 12.6 11.8 6.7 5.9 520 394 31.5 34.6 63.0
Max
964 9.6 82.7 17.7 16.1 9.1 7.5 528 398 40.6 66.9 3 7
c1 E E1 e L L1 y
protrusion .Allowable dambar protrusion shall not cause the lead width to exceed the maximum b3 dimension by more than 0.1 mm.
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eMCU writer list
Company Advantech 7F, No.98, Ming-Chung Rd., Shin-Tien City, Taipei, Taiwan, ROC Web site: http://www.aec.com.tw Caprilion P.O. Box 461 KaoHsiung, Taiwan, ROC Web site: http://www.market.net.tw/ ~ cap/ Hi-Lo 4F, No. 20, 22, LN, 76, Rui Guang Rd., Nei Hu, Taipei, Taiwan, ROC. Web site: http://www.hilosystems.com.tw Leap 6th F1-4, Lane 609, Chunghsin Rd., Sec. 5, Sanchung, Taipei Hsien, Taiwan, ROC Web site: http://www.leap.com.tw Xeltek Electronic Co., Ltd 338 Hongwu Road, Nanjing, China 210002 Web site: http://www.xeltek-cn.com Contact info Tel:02-22182325 Fax:02-22182435 E-mail: aecwebmaster@advantech.com.tw Programmer Model Number LabTool - 48 (1 * 1) LabTool - 848 (1*8)
Tel:07-3865061 Fax:07-3865421 E-mail: cap@market.net.tw
UNIV2000
Tel:02-87923301 Fax:02-87923285 E-mail: support@hilosystems.com.tw
All - 11 (1*1) Gang - 08 (1*8)
Tel:02-29991860 Fax:02-29990015 E-mail: service@leap.com.tw
ChipStation (1*1) SU - 2000 (1*8)
Tel:+86-25-4408399, 4543153-206 E-mail: xelclw@jlonline.com, xelgbw@jlonline.com
Superpro/2000 (1*1) Superpro/680 (1*1) Superpro/280 (1*1) Superpro/L+(1*1)
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